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Predicting system-level area and delay for pipelined and nonpipelined designs
Jain, R.; Parker, A.C.; Park, N.;
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Volume 11,
Issue 8,
Aug. 1992
Page(s):955
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965
Abstract:
The ability to predict area-delay characteristics of designs without actually implementing them is important in producing quality designs in a reasonable time. A mathematical model for predicting the area-delay tradeoff curve for pipelined and nonpipelined data paths, given a data flow graph and a choice of module styles, is proposed. The model has been validated against designs generated by pipelined and nonpipelined data-path synthesis programs
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