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Winter 1996 (Vol. 13, No. 4)   pp. 40-49
BIST for D/A and A/D Converters

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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.544535
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Abstract
A novel test approach and circuitry suitable for built-in self-test (BIST) of digital-to-analog (D/A) and analog-to-digital (A/D) converters using static parameters are proposed. Offset, gain, integral nonlinearity (INL) and differential nonlinearity (DNL) are tested without using mixed-mode or logic test equipment. The proposed BIST structure presents a compromise between area overhead (AO), test time, and fault coverage. The BIST circuitry has been designed and evaluated using CMOS 1.2-micron technology. The simulations show that, assuming the BIST voltage references fulfill the required accuracy, the BIST structure is applicable for testing D/A and A/D converters up to 16-bits of resolution. By only a minor modification, the test structure would be able to localize the fail situation and to test all D/A converters on the same chip. The small value of AO, the simplicity and efficiency of the proposed BIST architectures seem to be promising for manufacturing.
References
[1] K. Arabi, B. Kaminska, and J. Rzeszut, "A New Built-In Self-Test Approach for Digital-to-Analog and Analog-to-Digital Converters," IEEE/ACM Int'l Conf. on CAD-94, Digest of Technical Papers, IEEE Computer Society Press, Los Alamitos, Calif., 1994, pp. 491-494.
[2] M.F. Toner and G.W. Roberts, "A BIST Scheme for an SNR Test of a Sigma-Delta ADC," Proc. Int'l Test Conf., IEEE CS Press, 1993, pp. 805-814.
[3] J.R. Naylor, "Testing Digital/Analog and Analog/Digital Converters," IEEE Trans. Circuits and Systems, Vol. CAS-25, No. 7, July 1978, pp. 526-538.
[4] P.P. Fasang, D. Mulins, and T. Wong, "Design for Testability for Mixed Analog/Digital ASICs," Proc. IEEE Custom Integrated Circuit Conf., IEEE, Piscataway, N.J., 1988, pp. 16.5.1-16.5.4.
[5] M. Soma, "A Design-for-Test Methodology for Active Analog Filters," Proc. Int'l Test Conf., IEEE Computer Society Press, Los Alamitos, Calif., 1990, pp. 183-192.
[6] K.D. Wagner and T.W. Williams, "Design for Testability of Mixed Signal Integrated Circuits," Proc. Int'l Test Conf., IEEE CS Press, 1988, pp. 823-829.
[7] S. Max, "Fast, Accurate and Complete ADC Testing," Proc. Int'l Test Conf., IEEE CS Press, 1989, pp. 598-640.
[8] T.M. Souders and D.R. Flach, "An Automated Test Set for High Resolution Analog-to-Digital and Digital-to-Analog Converters," IEEE Trans. Instrumentation and Measurement, Vol. IM-28, No. 4, Dec. 1979, pp. 239-244.
[9] E. Teraoca et al., "A Built-In Self-Test for ADC and DAC in a Single-Chip Speech CODEC," Proc. Int'l Test Conf., IEEE CS Press, 1993, pp. 791-796.
[10] R. Bobba et al., "Fast Embedded A/D Converter Testing Using the Microcontroller's Resources," Proc. Int'l Test Conf., IEEE CS Press, 1990, pp. 598-604.
[11] C. Browing, "Testing A/D Converters on Microprocessors," Proc. Int'l Test Conf., IEEE CS Press, 1985, pp. 818-824.
[12] M. Song, Y. Lee, and W. Kim, "A Clock Feedthrough Reduction Circuit for Switched-Current Systems," IEEE J. of Solid-State Circuits, Vol. 28, No. 2, Feb. 1993, pp. 133-137.
Additional Information

Citation:  Karim Arabi, Bozena Kaminska, Janusz Rzeszut, "BIST for D/A and A/D Converters," IEEE Design and Test of Computers, vol. 13,  no. 4,  pp. 40-49,  Winter,  1996

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