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Published Articles >> Table of Contents >> Abstract
January-March 1999 (Vol. 16, No. 1)
pp. 53-58
Universal Test Interface for Embedded-DRAM Testing
Shinji Miyano
Katsuhiko Sato
Kenji Numata
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.748805
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| Abstract |
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This paper describes circuitry for facilitating the test of embedded DRAM macro whose configuration can be easily changed (reconfigurable macro). It is difficult to use conventional direct access mode circuitry, because the configuration of embedded DRAMs on a chip is varied for each product, and therefor the test circuitry should be customized for each product. The proposed test circuits implemented in the macro provide a Universal Test Interface regardless of the DRAM configuration and the number of macros on a chip.
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 References
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[1] S. Miyano et al., "A 1.6 GB/s Data-Transfer-Rate 8Mb Embedded DRAM," IEEE J. Solid-State Circuits, Vol. 30, No 11, Nov. 1995, pp. 1281-1285.
[2] T. Yabe et al., "A Configurable DRAM Macro Design for 2112 Derivative Organizations to Be Synthesized Using a Memory Generator," Digest of Technical Papers, IEEE Int'l Solid-State Circuits Conf., IEEE, Piscataway, N.J., 1998, pp. 72-73.
[3] J. Dreibelbis, "An ASIC Library Granular DRAM Macro with Built-In Self-Test," Digest of Technical Papers, Int'l Solid-State Circuits Conf., 1998, pp. 74-75.
[4] K. Sawada et al., "A 72k CMOS Channelless Gate Array with Embedded 1Mbit Dynamic RAM," Digest of Technical Papers, IEEE Custom Integrated Circuits Conf., IEEE, Piscataway, N.J., 1988, pp. 20.3.1-20.3.4.
[5] T. Watanabe et al., "A Modular Architecture for a 6.4Gbyte/s, 8Mbit Media Chip," Digest of Technical Papers, Symp. VLSI Circuits, IEEE, Piscataway, N.J., 1996, pp. 42-43.
[6] P. Gillingham et al., "A 768K Embedded DRAM for 1.244Gb/s ATM Switch in a 0.8μm Logic Process," Digest of Technical Papers, Int'l Solid-State Circuits Conf., 1996, pp. 262-263.
[7] H. Takeuchi et al., "A DRAM Module Generator with an Expandable Cell Array Scheme" Proc. IEEE Custom Integrated Circuits Conf., IEEE, Piscataway, N.J., 1998, pp. 287-290.
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 Additional Information
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Index Terms- Embedded DRAM, Direct Access Mode, Universal Test Interface, BIST
Citation:
Shinji Miyano, Katsuhiko Sato, Kenji Numata,
"Universal Test Interface for Embedded-DRAM Testing,"
IEEE Design and Test of Computers,
vol. 16,
no. 1,
pp. 53-58,
Jan-Mar,
1999
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