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Mesh routing topologies for multi-FPGA systems
Hauck, S.; Borriello, G.; Ebeling, C.;
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Volume 6,
Issue 3,
Sept. 1998
Page(s):400
-
408
Abstract:
There is currently great interest in using fixed arrays of FPGAs for logic emulators, custom computing devices, and software accelerators. An important part of designing such a system is determining the proper routing topology to use to interconnect the FPGAs. This topology can have a great effect on the area and delay of the resulting system. Crossbar, Hierarchical Crossbar, and Mesh interconnection schemes have all been proposed for use in FPGA-based systems. In this paper, we examine Mesh interconnection schemes, and propose several constructs for more efficient topologies. These reduce interchip delays by more than 60% over the basic four-way Mesh
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