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Published Articles >> Table of Contents >> Abstract
Seventh International Conference on Application of Concurrency to System Design (ACSD 2007)
pp. 120-126
Platform-scalable Task Partition and Multilevel Buffering in Multi-processor Plessey Corner Detector
Guan Yu, Vrije Universiteit Brussel, Belgium; Inter-university Micro-Electronics Centre, Belgium
Gauthier Lafruit, Inter-university Micro-Electronics Centre, Belgium
Peter Schelkens, Universiteit Brussel, Belgium
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ACSD.2007.58
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| Abstract |
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The Plessey corner detector is a key technological
component in scene analysis, stereo matching, and
object tracking. Due to its high computation complexity,
earlier fast implementations mainly focused on
hardware implementations. This paper explores the
viability of a multi-processor software implementation.
A scalable task partitioning for efficiently mapping the
Plessey algorithm on a multi-processor platform is
proposed. The task partition ensures platform
scalability, low inter-processor communication
overhead and a well-balanced workload in each task. In
addition, a multilevel buffering scheme is presented,
minimizing the external memory accesses in each task to
one image pixel read per calculated corner response
value. The effectiveness of the proposed task partition
and buffering scheme has been verified on (i) a cycle
accurate simulator with shared memory and (ii) a
multiple-TI-C64 DSP board using a message passing
paradigm. The proposed solution combines good
platform scalability with an additional 30% speedup
gain over straightforward parallelization schemes.
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 Additional Information
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Citation:
Guan Yu, Gauthier Lafruit, Peter Schelkens,
"Platform-scalable Task Partition and Multilevel Buffering in Multi-processor Plessey Corner Detector,"
acsd,
pp. 120-126,
Seventh International Conference on Application of Concurrency to System Design (ACSD 2007),
2007
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