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Published Articles >> Table of Contents >> Abstract
40th Annual Simulation Symposium (ANSS'07)
pp. 247-255
An Accurate and Efficient Time-Division Parallelization of Cycle Accurate Architectural Simulators
Masahiro Yano, Toyohashi University of Technology, Japan
Toru Takasaki, Toyohashi University of Technology, Japan
Takashi Nakada, Toyohashi University of Technology, Japan
Hiroshi Nakashima, Kyoto University, Japan
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ANSS.2007.9
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| Abstract |
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This paper proposes a parallel cycle-accurate microarchitectural
simulator which efficiently executes its workload
by splitting the simulation process along time-axis into
many intervals. This time-division parallelization is similar
to the concept of trace-splitting parallelization but is completely
different from this conventional technique because
our simulator assures that its result is perfectly equivalent
to what a sequential simulator produces. The assurance of
the perfect accuracy is endued by a simple failure recovery
mechanism; if i-th interval is simulated by a node with
an approximate initial machine state which causes invalid
result, the interval is simulated again by the node responsible
to (i-1)-th interval and thus having the correct state
at the beginning of i-th interval. In order to reduce the possibility
of the interval failure for efficiency, the fully cycleaccurate
simulation for an interval is preceded by a partial
and thus fast microarchitectural simulation including that
for caches, branch predictors and their interaction in speculative
execution. Another important technique is to check
the validity of an interval simulation by comparing approximate
and correct initial states with respect to their effect
to the subsequent execution, rather than the raw values of
them. The effectiveness of these techniques are exhibited by
our SimpleScalar-based implementation and its evaluation
with SPEC CPU95 benchmarks which results that 8-node
and 16-node parallel simulations achieve up to 5.8-fold and
9.4-fold speedup respectively.
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 Additional Information
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Citation:
Masahiro Yano, Toru Takasaki, Takashi Nakada, Hiroshi Nakashima,
"An Accurate and Efficient Time-Division Parallelization of Cycle Accurate Architectural Simulators,"
anss,
pp. 247-255,
40th Annual Simulation Symposium (ANSS'07),
2007
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