Abstract
In this paper we deal with the polynomial evaluation based on new processor architectures for multimedia applications. We introduce some algorithms to take advantage of the new attributes on multimedia processors, such as VLIW and SIMD architectures. Algorithms to support the polynomial evaluation based only in addition/shift operations and other different algorithms with MAC instructions are analyzed and tailored to subword parallelism units of the new processors. Both potential instruction-level and machine-level parallelism are fully exploited through concurrent use of all functional units.