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2007 Asia and South Pacific Design Automation Conference   pp. 96-97
A 2.8-V Multibit Complex Bandpass ¿¿AD Modulator in 0.18¿m CMOS

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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2007.357958
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Abstract
A second-order multibit switched-capacitor (SC) complex bandpass DeltaSigma AD modulator has been designed, fabricated and tested for application to low-IF receivers in wireless communication systems. We have employed two new algorithms there to improve the signal-to-noise-and-distortion (SNDR) of the modulator, (i) A complex bandpass filter with I, Q dynamic matching to reduce the mismatch influence between I, Q paths. As its by-product, the complex modulator can be divided into two separate parts without signal line crossing between the upper and lower paths. Therefore, the layout design of the modulator can be greatly simplified; (ii) A new complex bandpass data-weighted averaging (DWA) algorithm is implemented to suppress nonlinearity effects of multibit DACs in complex form to achieve high accuracy. Implemented in a 0.18-mum CMOS process and at 2.8V supply, the modulator achieves a measured peak SNDR of 64.5dB at 20MS/s with a signal bandwidth of 78kHz while dissipating 28.4mW and occupying an area of 1.82mm2.
Additional Information
Index Terms- 2.8 V, bandpass delta-sigma AD modulator, second-order AD modulator, multibit switched-capacitor AD modulator, low-IF receivers, wireless communication systems, signal-to-noise-and-distortion, complex bandpass filter, dynamic matching, data-weighted averaging algorithm, CMOS process, 78 kHz, 28.4 mW, 0.18 micron

Citation:  H. San, Y. Jingu, H. Wada, H. Hagiwara, A. Hayakawa, H. Kobayashi, M. Hotta, "A 2.8-V Multibit Complex Bandpass ¿¿AD Modulator in 0.18¿m CMOS," asp-dac, pp. 96-97,  2007 Asia and South Pacific Design Automation Conference,  2007

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