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Published Articles >> Table of Contents >> Abstract
21st International Conference on Distributed Computing Systems Workshops (ICDCSW '01)
p. 0255
LART: Flexible, Low-Power Building Blocks for Wearable Computers
Jan-Derk Bakker, Delft University of Technology
Koen Langendoen, Delft University of Technology
Henk Sips, Delft University of Technology
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/CDCS.2001.918714
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Abstract: To ease the implementation of different wearable computers, we developed a low-power processor board (named LART) with a rich set of interfaces. The LART supports dynamic voltage scaling, so performance (and power consumption) can be scaled to match demands: 59-221 MHz, 106-640 mW. High-end wearables can be configured from multiple LARTs operating in parallel; alternatively, FPGA boards can be used for dedicated data-processing, which reduces power consumption significantly.
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 Additional Information
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Citation:
Jan-Derk Bakker, Koen Langendoen, Henk Sips,
"LART: Flexible, Low-Power Building Blocks for Wearable Computers,"
icdcsw,
p. 0255,
21st International Conference on Distributed Computing Systems Workshops (ICDCSW '01),
2001
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