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Published Articles >> Table of Contents >> Abstract
International Symposium on Code Generation and Optimization (CGO'06)
pp. 245-255
Post Register Allocation Spill Code Optimization
Christopher Lupo, University of California, Davis, CA
Kent D. Wilken, University of California, Davis, CA
Full Article Text:
 
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/CGO.2006.28
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| Abstract |
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A highly optimized register allocator should provide an
efficient placement of save/restore code for procedures that
contain calls. This paper presents a new approach to placing
callee-saved save and restore instructions that generalizes
Chow’s shrink-wrapping technique[6]. An efficient,
profile-guided, hierarchical spill code placement algorithm
is used to analyze the structure of a procedure to calculate
the minimum dynamic execution count locations to place
callee-saved save and restore code. The algorithm is implemented
in the Gnu Compiler Collection and has been
tested on the SPEC CPU2000 Integer Benchmark suite. Results
show that the technique reduces the number of dynamic
load and store instructions by 15% compared to saving
and restoring at procedure entry and exit while Chow’s
shrink-wrapping technique reduces dynamic load and store
instructions by only 1% compared to saving and restoring
at procedure entry and exit. The dynamic number of calleesaved
save and restore instructions inserted with this new
approach is never greater than the number produced by
Chow’s shrink-wrapping technique or the placement at procedure
entry and exit.
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 Additional Information
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Citation:
Christopher Lupo, Kent D. Wilken,
"Post Register Allocation Spill Code Optimization,"
cgo,
pp. 245-255,
International Symposium on Code Generation and Optimization (CGO'06),
2006
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