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IEEE International Conference on Cluster Computing (CLUSTER'03)   p. 259
Implications of a PIM Architectural Model for MPI
Arun Rodrigues, University of Notre Dame
Richard Murphy, University of Notre Dame
Peter Kogge, University of Notre Dame
Jay Brockman, University of Notre Dame
Ron Brightwell, Sandia National Labs
Keith Underwood, Sandia National Labs

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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/CLUSTR.2003.1253323
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Abstract
Memory may be the only system component that is more commoditized than a microprocessor. To simultaneously exploit this and address the impending memory wall, processing in memory (PIM) research efforts are considering ways to move processing into memory without significantly increasing the cost of the memory. As such, PIM devices may become the basis for future commodity clusters. Although these PIM devices may leverage new computational paradigms such as hardware support for multi-threading and traveling threads, they must provide support for legacy programming models if they are to supplant commodity clusters. This paper presents a prototype implementation of MPI over a traveling thread mechanism called parcels. A performance analysis indicates that the direct hardware support of a traveling thread model can lead to an efficient, lightweight MPI implementation.
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Citation:  Arun Rodrigues, Richard Murphy, Peter Kogge, Jay Brockman, Ron Brightwell, Keith Underwood, "Implications of a PIM Architectural Model for MPI," cluster, p. 259,  IEEE International Conference on Cluster Computing (CLUSTER'03),  2003