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Design, Automation and Test in Europe (DATE'05) Volume 1   pp. 164-169
Specification Test Compaction for Analog Circuits and MEMS
Sounil Biswas, Carnegie Mellon University, Pittsburgh, PA
Peng Li, Texas A&M University, College Station
R. D. (Shawn) Blanton, Carnegie Mellon University, Pittsburgh, PA
Larry T. Pileggi, Carnegie Mellon University, Pittsburgh, PA

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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2005.277
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Abstract
Testing a non-digital integrated system against all of its specifications can be quite expensive due to the elaborate test application and measurement setup required. We propose to eliminate redundant tests by employing ε-SVM based statistical learning. Application of the proposed methodology to an operational amplifier and a MEMS accelerometer reveal that redundant tests can be statistically identified from a complete set of specification-based tests with negligible error. Specifically, after eliminating five of eleven specification-based tests for an operational amplifier, the defect escape and yield loss is small at 0.6% and 0.9%, respectively. For the accelerometer, defect escape of 0.2% and yield loss of 0.1% occurs when the hot and colt tests are eliminated. For the accelerometer, this level of Compaction would reduce test cost by more than half.
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Citation:  Sounil Biswas, Peng Li, R. D. (Shawn) Blanton, Larry T. Pileggi, "Specification Test Compaction for Analog Circuits and MEMS," date, pp. 164-169,  Design, Automation and Test in Europe (DATE'05) Volume 1,  2005