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Design, Automation and Test in Europe (DATE'05) Volume 1   pp. 36-42
Analog and Digital Circuit Design in 65 nm CMOS: End of the Road?
Georges Gielen, K.U. Leuven, Belgium
Wim Dehaene, K.U. Leuven, Belgium
Phillip Christie, Philips, The Netherlands
Dieter Draxelmayr, Infineon, Austria
Edmond Janssens, ST Microelectronics, Belgium
Karen Maex, IMEC, Belgium
Ted Vucurevich, Cadence, USA

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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2005.64
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Abstract
This special session adresses the problems that designers face when implementing analog and digital circuits in nanometer technologies. An introductory embedded tutorial will give an overview of the design problems at hand : the leakage power and process variability and their implications for digital circuits and memories, and the reducing supply voltages, the design productivity and signal integrity problems for embedded analog blocks. Next, a panel of experts from both industrial semiconductor houses and design companies, EDA vendors and research institutes will present and discuss with the audience their opinions on whether the design road ends at marker "65nm" or not.
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Citation:  Georges Gielen, Wim Dehaene, Phillip Christie, Dieter Draxelmayr, Edmond Janssens, Karen Maex, Ted Vucurevich, "Analog and Digital Circuit Design in 65 nm CMOS: End of the Road?," date, pp. 36-42,  Design, Automation and Test in Europe (DATE'05) Volume 1,  2005