| Abstract |
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This paper presents a high speed low voltage differential signal (LVDS) interface circuit for CPU, LCD, FPGA and other fast links. In the proposed transmitter a stabile reference and a common mode feedback circuit are applied into the LVDS drivers, which enable the transmitter to tolerate the variations of process, temperature and supply voltage. The proposed receiver implements a rail-to-rail amplifier architecture which allows a 1.6G b/s transmission. The transmitter and receiver are implemented in HJ TC 3.3 v, 0.18 µ CMOS technology. Transmission operations up to 1.6 Gb/s with random data patterns were demonstrated. The transmitter and receiver pad cells exhibit a power consumption of 35 mW and 6 mW respectively.
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 Additional Information
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Index Terms- LVDS rail-to-rail
Citation:
Feng Zhang, Zongren Yang, Wei Feng, Hao Cui, Lingyi Huang, Weiwu Hu,
"A High Speed CMOS Transmitter and Rail-to-Rail Receiver,"
delta,
pp. 67-70,
4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008),
2008
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