| Abstract |
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A 14-bit, 320 MSPS digital-to-analog converter is designed for high-speed applications. Considering the trade-off among linearity, dynamic performance, chip area, and power dissipation, the proposed DAC employs 5+4+5 segmented structure. The paper focuses on the design of several key circuits, and presents the experiment results (DNL=±2.0 LSB ,INL=±2.7 LSB, SFDR=72.6 dB @ fdata=320 MSPS,fout=4.375 MHz) based on the SMIC 0.35µm Mixed Signal 2P3M CMOS process model. The chip has been fabricated in the SMIC 3.3 V technology with an active area of 2.6×2.6 mm2.
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 Additional Information
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Index Terms- segmented current-steering, pseudorandom switching sequence, current switch driving circuit, unit current-cell
Citation:
Liang Shangquan, Gao Minglun, Yin Yongsheng, Deng Honghui,
"A 14-bit 320 MSPS Segmented Current-Steering D/A Converter for High-Speed Applications,"
delta,
pp. 111-114,
4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008),
2008
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