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UML Based Reverse Engineering for the Verification of Railway Control Logics
International Conference on Dependabi ...
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Chiara Abbaneo, ANSALDO SIGNAL, Naples, Italy
Francesco Flammini, Universita Federico II di Napoli, Italy
Armando Lazzaro, ANSALDO SIGNAL, Naples, Italy
Pietro Marmo, ANSALDO SIGNAL, Naples, Italy
Nicola Mazzocca, Universita "Federico II" di Napoli, Italy
Angela Sanseviero, ANSALDO SIGNAL, Naples, Italy
The Unified Modeling Language (UML) is widely used as a high level object oriented specification language. In this paper we present a novel approach in which reverse engineering is performed using UML as the modelling language used to achieve a representation of the implemented system. The target is the core logic of a complex critical railway control system, which was written in an application specific legacy language. UML perfectly suited to represent the nature of the core logic, made up by concurrent and interacting processes, using a bottom-up approach and proper modeling rules. Each process, in fact, was strictly related to the management of a physically (resp. logically) well distinguished railway device (resp. functionality). The obtained model deeply facilitated the static analysis of the logic code, allowing for at a glance verification of correctness and compliance with higher-level specifications, and opened the way to refactoring and other formal analyses.
Citation:
Chiara Abbaneo, Francesco Flammini, Armando Lazzaro, Pietro Marmo, Nicola Mazzocca, Angela Sanseviero, "UML Based Reverse Engineering for the Verification of Railway Control Logics," depcos-relcomex,pp.3-10, International Conference on Dependability of Computer Systems (DEPCOS-RELCOMEX'06), 2006
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