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Design and Evaluation of a Hardware on-line Program-Flow Checker for Embedded Microcontrollers
21st IEEE International Symposium on ...
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M. Ottavi, Northeastern University Boston, USA
S. Pontarelli, Universit? di Roma "Tor Vergata", Italy
A. Leandri, Universit? di Roma "Tor Vergata", Italy
A. Salsano, Universit? di Roma "Tor Vergata", Italy
This paper investigates the effects of a class of transient faults, the so-called Single Event Upsets, on the execution of programs in typical microcontroller architecture as can be found on a system on chip for embedded applications. It is observed that the consequences of targeting the registers used in the control flow can cause unexpected jumps of the program and consequent heavy effects on the results or the freeze of the microcontroller. A novel hardware based control flow checker is then introduced and implemented on an FPGA test bed together with the microcontroller core and fault injection circuitry. The FPGA implementation allows to dynamically and quickly injecting faults on the microcontroller whereas the results of the fault injection campaign allow to evaluate the fault coverage of the proposed method with a high degree of flexibility.
Citation:
M. Ottavi, S. Pontarelli, A. Leandri, A. Salsano, "Design and Evaluation of a Hardware on-line Program-Flow Checker for Embedded Microcontrollers," dft,pp.371-379, 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'06), 2006
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