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Gate Failures Effectively Shape Multiplexing

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DFT.2006.33

21st IEEE International Symposium on ...

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	ASCII Text	x
	V. Beiu, W. Ibrahim, Y.A. Alkhawwar, M.H. Sulieman, "Gate Failures Effectively Shape Multiplexing," Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on, vol. 0, no. 0, pp. 29-40, 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'06), 2006.

	BibTex	x
	@article{ 10.1109/DFT.2006.33, author = {V. Beiu and W. Ibrahim and Y.A. Alkhawwar and M.H. Sulieman}, title = {Gate Failures Effectively Shape Multiplexing}, journal ={Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on}, volume = {0}, year = {2006}, issn = {1550-5774}, pages = {29-40}, doi = {http://doi.ieeecomputersociety.org/10.1109/DFT.2006.33}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on TI - Gate Failures Effectively Shape Multiplexing SN - 1550-5774 SP29 EP40 A1 - V. Beiu, A1 - W. Ibrahim, A1 - Y.A. Alkhawwar, A1 - M.H. Sulieman, PY - 2006 KW - null VL - 0 JA - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on ER -

V. Beiu, United Arab Emirates University, United Arab Emirates

W. Ibrahim, United Arab Emirates University, United Arab Emirates

Y.A. Alkhawwar, United Arab Emirates University, United Arab Emirates

M.H. Sulieman, United Arab Emirates University, United Arab Emirates

This paper investigates the behavior of multiplexing (MUX) schemes in combination with the elementary gates. The two schemes under investigation are majority (MAJ) and NAND MUX. The simulation results presented here are for single-electron technology, but could easily be extended to CMOS. The components of the gates have been subjected only to geometric variations. Firstly, the gates and the two MUX schemes are analyzed theoretically. Secondly, simulations using probability transfer matrices (PTM) allow evaluating both MUX schemes at a redundancy factor R = 6. Finally, the gates are compared in terms of their intrinsic probability of failure (with respect to geometric variations), and the two MUX schemes are weighted against the reliability enhancements they are bringing into the system. By comparing the simulation results from PTM with the ones based on (geometric) variations, this study gives deeper insights into the behavior of MUX schemes, and show that the gates play a major role, strongly affecting MUX systems.

Citation:

V. Beiu, W. Ibrahim, Y.A. Alkhawwar, M.H. Sulieman, "Gate Failures Effectively Shape Multiplexing," dft,pp.29-40, 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'06), 2006

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