Digital Library

Improving Yield and Defect Tolerance in Multifunction Subthreshold CMOS Gates

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DFT.2006.35

21st IEEE International Symposium on ...

	This Article
	PURCHASE ARTICLE: $19 PDF HTML IEEE Xplore Subscribers
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Kristian Granhaug Articles by Snorre Aunet

	ASCII Text	x
	Kristian Granhaug, Snorre Aunet, "Improving Yield and Defect Tolerance in Multifunction Subthreshold CMOS Gates," Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on, vol. 0, no. 0, pp. 20-28, 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'06), 2006.

	BibTex	x
	@article{ 10.1109/DFT.2006.35, author = {Kristian Granhaug and Snorre Aunet}, title = {Improving Yield and Defect Tolerance in Multifunction Subthreshold CMOS Gates}, journal ={Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on}, volume = {0}, year = {2006}, issn = {1550-5774}, pages = {20-28}, doi = {http://doi.ieeecomputersociety.org/10.1109/DFT.2006.35}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on TI - Improving Yield and Defect Tolerance in Multifunction Subthreshold CMOS Gates SN - 1550-5774 SP20 EP28 A1 - Kristian Granhaug, A1 - Snorre Aunet, PY - 2006 KW - null VL - 0 JA - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on ER -

Kristian Granhaug, University of Oslo, Norway

Snorre Aunet, University of Oslo, Norway

This paper presents simulations of 3 different implementations of the minority-3 function, with special focus on mismatch analysis through statistical Monte Carlo-simulations. The simulations clearly favors the minority-3 Mirrored gate, and a gate-level redundancy scheme, where identical circuits with the same input drive the same output-node, is further explored as a means of increasing fault- and defect-tolerance. Important tradeoffs between supply voltage, redundancy and yield are revealed, and V_D_D = 175 mV is suggested as a minimum useful operating voltage, combined with a redundancy factor of 2.

Citation:

Kristian Granhaug, Snorre Aunet, "Improving Yield and Defect Tolerance in Multifunction Subthreshold CMOS Gates," dft,pp.20-28, 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'06), 2006

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.

				Searching...	Advanced Search
	CS Search		Google Search