|
Published Articles >> Table of Contents >> Abstract
8th Euromicro Conference on Digital System Design (DSD'05)
pp. 17-25
Functional Vectors Generation for RT-Level Verilog Descriptions Based on Path Enumeration and Constraint Logic Programming
Tun Li, National University of Defense Technology, China
Yang Guo, National University of Defense Technology, China
GongJie Liu, National University of Defense Technology, China
SiKun Li, National University of Defense Technology, China
Full Article Text:
 
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DSD.2005.43
Send link to a friend
| Abstract |
|
This paper presents a novel method for automatic
functional vectors generation from RT-Level HDL
descriptions based on path coverage and constraint
solving. Compared with existing method, the advantage
of this method includes: 1) it avoids generating
redundant constraints, which will accelerate the test
generation process. 2) it solves the problem of how to
propagate the internal values to the primary inputs with
decision models. 3) it can handle various HDL
description styles, and various styles of designs.
Experimental results conduct on several practical
designs show that our method can efficiently improve
the functional vectors generation process. The prototype
system has been applied to verify RTL description of a
real 32-bits microprocessor core and complex bugs
remained hidden in the RTL descriptions are detected.
|
 Additional Information
|
Citation:
Tun Li, Yang Guo, GongJie Liu, SiKun Li,
"Functional Vectors Generation for RT-Level Verilog Descriptions Based on Path Enumeration and Constraint Logic Programming,"
dsd,
pp. 17-25,
8th Euromicro Conference on Digital System Design (DSD'05),
2005
|
|
