This paper presents our contribution in terms of synchronization processor to a SoC design methodology based on the theory of latency insensitive systems (LIS). This methodology 1) promotes pre-developed IPs intensive reuse, 2) segments inter-IP interconnects with relay stations to break critical paths and 3) brings robustness to data stream irregularities to IPS by encapsulation into a synchronization wrapper. Our contribution consists in IP encapsulation into a new wrapper model containing a synchronization processor, which speed and area are optimized and synthesizability guarantied. The main benejit of our approach is to preserve the local IP performances when encapsulating them. This approach is part of the RNRT ALIPTA project, which targets design automation of intensive digital signal processing systems with GA UT [l], a high-level synthesis tool.