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Published Articles >> Table of Contents >> Abstract
9th EUROMICRO Conference on Digital System Design (DSD'06)
pp. 97-106
A Monitoring-Aware Network-on-Chip Design Flow
Calin Ciordas, Eindhoven University of Technology, The Netherlands
Andreas Hansson, Eindhoven University of Technology, The Netherlands
Kees Goossens, Philips Research Laboratories Eindhoven, The Netherlands
Twan Basten, Eindhoven University of Technology, The Netherlands
Full Article Text:
 
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DSD.2006.11
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| Abstract |
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Networks-on-chip (NoC) are a scalable interconnect solution
for systems on chip and are rapidly becoming reality.
Monitoring is a key enabler for debugging or performance
analysis and quality-of-service techniques. The NoC design
problem and the NoC monitoring problem cannot be treated
in isolation. We propose a monitoring-aware NoC design
flow able to take into account the monitoring requirements
in general. We illustrate our flow with a debug driven monitoring
case study of transaction monitoring. By treating the
NoC design and monitoring problems in synergy, the area
cost of monitoring can be limited to 3-20% in general.
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 Additional Information
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Citation:
Calin Ciordas, Andreas Hansson, Kees Goossens, Twan Basten,
"A Monitoring-Aware Network-on-Chip Design Flow,"
dsd,
pp. 97-106,
9th EUROMICRO Conference on Digital System Design (DSD'06),
2006
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