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Evaluating Dataflow and Pipelined Vector Processing Architectures for FPGA Co-processors

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DSD.2006.51

9th EUROMICRO Conference on Digital S ...

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	ASCII Text	x
	Michael Freeman, "Evaluating Dataflow and Pipelined Vector Processing Architectures for FPGA Co-processors," Digital Systems Design, Euromicro Symposium on, vol. 0, no. 0, pp. 127-130, 9th EUROMICRO Conference on Digital System Design (DSD'06), 2006.

	BibTex	x
	@article{ 10.1109/DSD.2006.51, author = {Michael Freeman}, title = {Evaluating Dataflow and Pipelined Vector Processing Architectures for FPGA Co-processors}, journal ={Digital Systems Design, Euromicro Symposium on}, volume = {0}, year = {2006}, isbn = {}, pages = {127-130}, doi = {http://doi.ieeecomputersociety.org/10.1109/DSD.2006.51}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Digital Systems Design, Euromicro Symposium on TI - Evaluating Dataflow and Pipelined Vector Processing Architectures for FPGA Co-processors SN - SP127 EP130 A1 - Michael Freeman, PY - 2006 KW - null VL - 0 JA - Digital Systems Design, Euromicro Symposium on ER -

Michael Freeman, University of York, UK

This paper describes the development of a FPGA based co-processor architecture for accelerating vector comparisons e.g. Euclidean distance. In this paper we will compare traditional pipelined and dataflow implementations, in terms of processing speed and area requirements. Processing performance will then be compared against a software implementation to evaluate possible speedup.

Citation:

Michael Freeman, "Evaluating Dataflow and Pipelined Vector Processing Architectures for FPGA Co-processors," dsd,pp.127-130, 9th EUROMICRO Conference on Digital System Design (DSD'06), 2006

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