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Published Articles >> Table of Contents >> Abstract
37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07)
pp. 196-205
Superscalar Processor Performance Enhancement through Reliable Dynamic Clock Frequency Tuning
1 Subramanian, Iowa State University, USA
1 Bezdek, Iowa State University, USA
1 Avirneni, Iowa State University, USA
1 Somani, Iowa State University, USA
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DSN.2007.90
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| Abstract |
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Synchronous circuits are typically clocked considering worst case timing paths so that timing errors are avoided under all circumstances. In the case of a pipelined processor, this has special implications since the operating frequency of the entire pipeline is limited by the slowest stage. Our goal, in this paper, is to achieve higher performance in superscalar processors by dynamically varying the operating frequency during run time past worst case limits. The key objective is to see the effect of overclocking on superscalar processors for various benchmark applications, and analyze the associated overhead, in terms of extra hardware and error recovery penalty, when the clock frequency is adjusted dynamically. We tolerate timing errors occurring at speeds higher than what the circuit is designed to operate at by implementing an efficient error detection and recovery mechanism. We also study the limitations imposed by minimum path constraints on our technique. Experimental results show that an average performance gain up to 57% across all benchmark applications is achievable.
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 Additional Information
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Index Terms- Superscalar processor, Dynamic, overclocking, Fault-Tolerant Computing, Reliability.
Citation:
1 Subramanian, 1 Bezdek, 1 Avirneni, 1 Somani,
"Superscalar Processor Performance Enhancement through Reliable Dynamic Clock Frequency Tuning,"
dsn,
pp. 196-205,
37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07),
2007
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