In this work, our goal is to develop a flexible CAD tool by which designers can explore integration of different types of embedded hard cores and interfaces in the FPGA architectures. Our tool takes a RTL design and defined embedded hard cores. We have modified VPR for place and route with embedded blocks. We have experimented different modules to be embedded as hard cores on a FPGA device. We also explore the FPGA routing architecture with embedded hard cores by applying uniform and non-uniform routing channels. In many cases, non-uniform channels produce more area-efficient architectures. Our results show that there is a need for a tool for better exploration of design space for FPGAs with embedded hard cores.