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Published Articles >> Table of Contents >> Abstract
12th IEEE International On-Line Testing Symposium (IOLTS'06)
pp. 31-36
Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor
Swaroop Ghosh, Purdue University, USA
Swarup Bhunia, Purdue University, USA
Arijit Raychowdhury, Purdue University, USA
Kaushik Roy, Purdue University, USA
Full Article Text:
 
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IOLTS.2006.19
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| Abstract |
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Delay failures are becoming a dominant failure
mechanism in nanometer technologies. Diagnosis of such failures
is important to ensure yield and robustness of the design.
However, the increasing circuit size limits the granularity of
diagnosis, resulting in large suspect fault list. In this paper, we
present a methodology for improving delay fault localization
in test-per-scan BIST using on-die delay sensing at selective
test points. It is demonstrated that the proposed technique can
improve the resolution of fault localization for both transition
and segment delay fault models. Experimental results for a
set of ISCAS89 benchmarks show upto 49% (82%) average
improvement in fault localization for transition (segment) delay
fault models. The area overhead due to delay sensing hardware
have been limited to 4%.
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 Additional Information
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Index Terms- Test-per-scan BIST, delay sensor, fault diagnosis,
fault localization, test point insertion.
Citation:
Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy,
"Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor,"
iolts,
pp. 31-36,
12th IEEE International On-Line Testing Symposium (IOLTS'06),
2006
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