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19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Papers   p. 5a
Exploiting Barriers to Optimize Power Consumption of CMPs
Chun Liu, The Pennsylvania State University, University Park, PA
Anand Sivasubramaniam, The Pennsylvania State University, University Park, PA
Mahmut Kandemir, The Pennsylvania State University, University Park, PA
Mary Jane Irwin, The Pennsylvania State University, University Park, PA

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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IPDPS.2005.211
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Abstract
Power consumption is an important concern for future billion transistor designs. This paper proposes a novel technique for optimizing the power consumption of chip-multiprocessors (CMPs) using an integrated hardware-software mechanism. By using a high level synchronization construct, called the barrier, our technique tracks the idle times spent by a processor waiting for other processors to get to the same point in the program. Using this knowledge, the frequency of the processors can be modulated to reduce/eliminate these idle times, thus providing power savings without compromising on performance. Using real applications from the SpecOMP suite, and a complete system CMP simulator, we demonstrate that this approach can provide as much as 40% power savings (and 32% on the average across five applications) with little impact on performance.
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Citation:  Chun Liu, Anand Sivasubramaniam, Mahmut Kandemir, Mary Jane Irwin, "Exploiting Barriers to Optimize Power Consumption of CMPs," ipdps, p. 5a,  19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Papers,  2005