|
Published Articles >> Table of Contents >> Abstract
33rd International Symposium on Computer Architecture (ISCA'06)
pp. 41-52
Conditional Memory Ordering
Christoph von Praun, IBM T.J. Watson Research Center, Yorktown Heights, NY
Harold W. Cain, IBM T.J. Watson Research Center, Yorktown Heights, NY
Jong-Deok Choi, IBM T.J. Watson Research Center, Yorktown Heights, NY
Kyung Dong Ryu, IBM T.J. Watson Research Center, Yorktown Heights, NY
Full Article Text:

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISCA.2006.16
Send link to a friend
| Abstract |
|
Conventional relaxed memory ordering techniques follow
a proactive model: at a synchronization point, a processor
makes its own updates to memory available to other
processors by executing a memory barrier instruction, ensuring
that recent writes have been ordered with respect
to other processors in the system. We show that this
model leads to superfluous memory barriers in programs
with acquire-release style synchronization, and present a
combined hardware/software synchronization mechanism
called conditional memory ordering (CMO) that reduces
memory ordering overhead. CMO is demonstrated on a
lock algorithm that identifies those dynamic lock/unlock operations
for which memory ordering is unnecessary, and
speculatively omits the associated memory ordering instructions.
When ordering is required, this algorithm relies
on a hardware mechanism for initiating a memory ordering
operation on another processor.
Based on evaluation using a software-only CMO prototype,
we show that CMO avoids memory ordering operations
for the vast majority of dynamic acquire and release
operations across a set of multithreaded Java workloads,
leading to significant speedups for many. However, performance
improvements in the software prototype are hindered
by the high cost of remote memory ordering. Using empirical
data, we construct an analytical model demonstrating
the benefits of a combined hardware-software implementation.
|
Additional Information
|
Citation:
Christoph von Praun, Harold W. Cain, Jong-Deok Choi, Kyung Dong Ryu,
"Conditional Memory Ordering,"
isca,
pp. 41-52,
33rd International Symposium on Computer Architecture (ISCA'06),
2006
|
|