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Published Articles >> Table of Contents >> Abstract
Sixth International Symposium on Quality of Electronic Design (ISQED'05)
pp. 310-315
Combining System Level Modeling with Assertion Based Verification
Anat Dahan, IBM Haifa Research Lab, Haifa Israel
Daniel Geist, IBM Haifa Research Lab, Haifa Israel
Leonid Gluhovsky, IBM Haifa Research Lab, Haifa Israel
Dmitry Pidan, IBM Haifa Research Lab, Haifa Israel
Gil Shapir, IBM Haifa Research Lab, Haifa Israel
Yaron Wolfsthal, IBM Haifa Research Lab, Haifa Israel
Lyes Benalycherif, ST Microelectronics, Grenoble, France
Romain Kamdem, ST Microelectronics, Grenoble, France
Younes Lahbib, ST Microelectronics, Grenoble, France
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2005.32
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| Abstract |
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Assertion-Based Verification (ABV) using the PSL language is currently gaining acceptance as an essential method for functional verification of hardware. A basic technique to implement ABV is to embed temporal assertions in RTL code. This paper describes the use of a PSL-based ABV methodology in a C++-based system level modeling and simulation environment. We describe the considerations of porting a tool which translates PSL to VHDL/Verilog, to support C++, a language which was designed for software and does not have concurrent language constructs. The translation scheme is shown to be adaptable to all C-based environments. We exemplify the wide applicability of this scheme by detailing its successful deployment in a SystemC-based industrial System-on-Chip (SoC) project.
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Citation:
Anat Dahan, Daniel Geist, Leonid Gluhovsky, Dmitry Pidan, Gil Shapir, Yaron Wolfsthal, Lyes Benalycherif, Romain Kamdem, Younes Lahbib,
"Combining System Level Modeling with Assertion Based Verification,"
isqed,
pp. 310-315,
Sixth International Symposium on Quality of Electronic Design (ISQED'05),
2005
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