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Published Articles >> Table of Contents >> Abstract
7th International Symposium on Quality Electronic Design (ISQED'06)
pp. 723-728
Simultaneous Fine-grain Sleep Transistor Placement and Sizing for Leakage Optimization
Wang Yu, Tsinghua University, Beijing, China
Lin Hai, Tsinghua University, Beijing, China
Yang Huazhong, Tsinghua University, Beijing, China
Luo Rong, Tsinghua University, Beijing, China
Wang Hui, Tsinghua University, Beijing, China
Full Article Text:
 
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2006.117
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| Abstract |
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With the growing scaling of technology, leakage power
dissipation has become a critical issue of VLSI circuits
and systems designs. Multi-threshold CMOS leads to
about 10X leakage reduction in circuit standby mode. In
this paper, we reduce leakage current through fine-grain
sleep transistor (ST) insertion which makes it easier to
guarantee circuit functionality at high speed and
improves circuit noise margins [1]. We model the leakage
current reduction problem as a mixed-integer linear
programming (MLP) problem in order to simultaneously
choose where to add the sleep transistors and the sleep
transistors’ sizes optimally. The model is solved with both
continuous (MLP-C) and discrete (MLP-D) sleep
transistor size constraints. Furthermore a method to
speed up MLP-D model is introduced. Because of the
better circuit slack utilization, our experimental results
show that the MLP-C model can achieve 79.75%,
93.56%, 94.99% leakage saving when the circuit slow
down is 0%, 3%, 5% respectively. The MLP-C model also
achieves on average 74.79% less area penalty compared
to the conventional fixed slowdown method when the
circuit slowdown is 7%. The MLP-D model can achieve
similar leakage saving compared to the MLP-C model.
The MLP-CtoD method can speed up the MLP-D model
30X times with almost no difference in leakage reduction.
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 Additional Information
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Citation:
Wang Yu, Lin Hai, Yang Huazhong, Luo Rong, Wang Hui,
"Simultaneous Fine-grain Sleep Transistor Placement and Sizing for Leakage Optimization,"
isqed,
pp. 723-728,
7th International Symposium on Quality Electronic Design (ISQED'06),
2006
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