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Published Articles >> Table of Contents >> Abstract
7th International Symposium on Quality Electronic Design (ISQED'06)
pp. 85-91
Clock Distribution Architectures: A Comparative Study
C. Yeh, Apache Design Sol.
G. Wilke, UFRGS, Brazil
H. Chen, Synopsys, CA, USA
S. Reddy, Fujitsu Laboratories of America, Inc., CA, USA
H. Nguyen, Fujitsu Laboratories of America, Inc., CA, USA
T. Miyoshi, Fujitsu Laboratories of America, Inc., CA, USA
W. Walker, Fujitsu Laboratories of America, Inc., CA, USA
R. Murgai, Fujitsu Laboratories of America, Inc., CA, USA
Full Article Text:
 
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2006.33
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| Abstract |
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This paper evaluates and compares different clock architectures
such as mesh, tree and their hybrids, on several industrial designs.
The goal of our study is to gain a quantitative understanding
of engineering trade-offs between different architectures
with respect to clock skew, latency, timing uncertainty, and
power. This understanding will lead to guidelines for determining
the best clock architecture for the design specification and
constraints. To the best of our knowledge, no work has been published
on evaluating and comparing these architectures on real
industrial designs. Our study shows that mesh-based architectures
are better than tree architectures for skew (\le 1ps skew) and
are more robust to variations (18% reduction in timing uncertainty
as compared to tree). The power penalty associated with
a mesh as compared to a tree was found to be between 10-40%.
Use of multiple meshes can help reduce the power penalty.
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 Additional Information
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Citation:
C. Yeh, G. Wilke, H. Chen, S. Reddy, H. Nguyen, T. Miyoshi, W. Walker, R. Murgai,
"Clock Distribution Architectures: A Comparative Study,"
isqed,
pp. 85-91,
7th International Symposium on Quality Electronic Design (ISQED'06),
2006
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