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Published Articles >> Table of Contents >> Abstract
7th International Symposium on Quality Electronic Design (ISQED'06)
pp. 79-84
Fast Incremental Link Insertion in Clock Networks for Skew Variability Reduction
Anand Rajaram, University of Texas at Austin
David Z. Pan, University of Texas at Austin
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2006.66
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| Abstract |
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With the advent of sub-100nm VLSI technologies, variation
effects greatly increase the unwanted skew in Clock
Distribution Networks (CDNs), thereby reducing the performance
of the chip. Recent works on link based non-tree
CDN [1-4] propose cross-link insertion in a given clock tree
to reduce skew variation. However, the current methods suffer
from the drawback that they are empirical in nature, requiring
the user to experiment with different parameter values.
Also, the methods of [1-3] ignore the interaction between
the different links while selecting the links for insertion.
The method of [4] attempts to overcome this drawback
using a statistical link insertion methodology. However, [4]
is very slow even for relatively small circuits. In this paper,
we propose a fast link insertion methodology which does
not require selecting empirical parameters for link insertion.
Our method also incrementally considers the effect of previously
inserted links before choosing the next link. SPICE
based Monte Carlo simulations show that our approach obtains
comparable skew reduction to that of the existing approaches
while drastically reducing the time taken to obtain
a good link-based non-tree CDN.
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 Additional Information
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Citation:
Anand Rajaram, David Z. Pan,
"Fast Incremental Link Insertion in Clock Networks for Skew Variability Reduction,"
isqed,
pp. 79-84,
7th International Symposium on Quality Electronic Design (ISQED'06),
2006
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