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Published Articles >> Table of Contents >> Abstract
7th International Symposium on Quality Electronic Design (ISQED'06)
pp. 98-104
Interconnect and Thermal-aware Floorplanning for 3D Microprocessors
W.-L. Hung, Pennsylvania State University, University Park
G.M. Link, Pennsylvania State University, University Park
Yuan Xie, Pennsylvania State University, University Park
N. Vijaykrishnan, Pennsylvania State University, University Park
M. J. Irwin, Pennsylvania State University, University Park
Full Article Text:
 
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2006.77
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| Abstract |
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Interconnects are becoming an increasing problem from
both performance and power consumption perspective in future
technology nodes. The introduction of 3D chip architectures,
with their intrinsic capability of reducing wire length,
is one of the promising solutions to mitigate the interconnect
problem. While interconnect power consumption reduces
due to the adoption of 3D designs, the stacking of multiple
active layers leads to higher power densities. Thus, high
peak temperatures are of major concern in 3D designs. Consequently,
we present a thermal-aware floorplanner for 3D
architectures. In contrast to most prior work, our floorplanner
considers the interconnect power consumption in exploring
a thermal-aware floorplan. Our results show that excluding
interconnect power can result in peak temperatures
being underestimated by as much as 15oC in 90nm technology.
Finally, we demonstrate that our floorplanner is effective
in lowering peak temperatures using a microprocessor
design and four MCNC designs as benchmarks.
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 Additional Information
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Citation:
W.-L. Hung, G.M. Link, Yuan Xie, N. Vijaykrishnan, M. J. Irwin,
"Interconnect and Thermal-aware Floorplanning for 3D Microprocessors,"
isqed,
pp. 98-104,
7th International Symposium on Quality Electronic Design (ISQED'06),
2006
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