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Published Articles >> Table of Contents >> Abstract
8th International Symposium on Quality Electronic Design (ISQED'07)
pp. 225-228
A 8b 10Ms/s Low Power Pipelined A/D Converter
1 Yuan, San Jose State University, USA
1 Zhang, San Jose State University, USA
1 He, San Jose State University, USA
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2007.7
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This paper describes an 8-bit, 10 MSamples/second analog to digital converter, with 2V fully differential input range, which is implemented in TSMC 0.25ìm CMOS technology. It achieves low power dissipation of 25mW, and the chip area is 0.56mm2. Measured performance yields a very good VTC curve and a sine wave fitting curve for 200KHz input at 10Msample/s, DNL testing of -0.2LSB~0.75LSB; INL testing of -0.2LSB~0.65LSB, 44.62dB of SNDR (signal to noise plus distortion ratio) and ENOB of 7.12 bits.
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Citation:
1 Yuan, 1 Zhang, 1 He,
"A 8b 10Ms/s Low Power Pipelined A/D Converter,"
isqed,
pp. 225-228,
8th International Symposium on Quality Electronic Design (ISQED'07),
2007
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