A High Speed Multi -Input Comparator with Clocking-Charge Based for Low-Power Systems

Shih-Chang Hsia

doi:10.1109/IWSOC.2003.1213021

System-on-Chip for Real-Time Applications, International Workshop on

A High Speed Multi -Input Comparator with Clocking-Charge Based for Low-Power Systems

Year: 2003, Pages: 130

DOI Bookmark: 10.1109/IWSOC.2003.1213021

Authors

Shih-Chang Hsia, University of Science and Technology, Kaohsiung 824, Taiwan, R.O.C.

Abstract

Currently, a comparison function has been widely used for discrete signal processing. In this study, a novel comparison-cell is presented based on clocking concept. The advantages are that the circuit complexity can be largely reduced and the delay time becomes shorter. The prototype cell is designed for 4-bit comparison cell using Spice simulator. As comparisons with CMOS base, the complexity of proposed cell is reduced to one-third, and the circuit delay can be shortened to half. With a regular design, the prototype of 4?6 comparison circuit is implemented based on 4-bit basic cell. The chip core is about 0.9mm2 using UMC 0.5 um process.

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A High Speed Multi -Input Comparator with Clocking-Charge Based for Low-Power Systems

Authors

Abstract

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