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IEEE Computer Society Workshop on VLSI 2001   p. 0047
A Heterogeneous Multiprocessor Architecture for Low-Power Audio Signal Processing Applications
Özgün Paker, Technical University of Denmark
Jens Sparsø, Technical University of Denmark
Niels Haandbæk, Oticon A/S
Mogens Isager, Oticon A/S
Lars Skovby Nielsen, Oticon A/S

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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IWV.2001.923139
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Abstract
Abstract: This paper describes a low-power programmable DSP architecture that targets audio signal processing. The architecture can be characterized as a heterogeneous multi-processor consisting of small and simple instruction set processors called mini-cores that communicate using message passing. The processors are tailored for different classes of filtering algorithms (FIR, IIR, N-LMS etc.), and in a typical system the communication among processors occur at the sampling rate only. The processors are parameterized in word-size, memory-size, etc. and can be instantiated according to the needs of the application at hand using a normal synthesis based ASIC design flow. To give an impression of the size of a processor we mention that one of the FIR processors in a prototype design has 16 instructions, a 32 word x 16 bit program memory, a 64 word x 16 bit data memory and a 25 word x 16 bit coefficient memory. Early results obtained from the design of a prototype chip containing filter processors for a hearing aid application, indicate a power consumption that is an order of magnitude better than current state of the art low-power audio DSP's implemented using full-custom techniques. This is due to: (1) the small size of the processors and (2) a smaller instruction count for a given task.
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Citation:  Özgün Paker, Jens Sparsø, Niels Haandbæk, Mogens Isager, Lars Skovby Nielsen, "A Heterogeneous Multiprocessor Architecture for Low-Power Audio Signal Processing Applications," wvlsi, p. 0047,  IEEE Computer Society Workshop on VLSI 2001,  2001