| Abstract |
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Several recently proposed techniques including CPR (Checkpoint Processing and Recovery) and NoSQ (No Store Queue) rely on reference counting to manage physical registers. However, the register reference counting mechanism itself has received surprisingly little attention. This paper fills this gap by describing potential register reference counting schemes for NoSQ, CPR, and a hypothetical NoSQ/CPR hybrid. Although previously described in terms of binary counters, we find that reference counts are actually more naturally represented as matrices. Binary representations can be used as an optimization in specific situations.
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 Additional Information
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Index Terms- Micro-architecture implementation considerations, Superscalar, dynamically-scheduled, and statically-scheduled implementation
Citation:
Amir Roth,
"Physical Register Reference Counting,"
IEEE Computer Architecture Letters,
vol. 7,
no. 1,
pp. 9-12,
Jan-Jun,
2008
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