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Published Articles >> Table of Contents >> Abstract
July-December 2007 (Vol. 6, No. 2)
pp. 29-32
Microarchitectures for Managing Chip Revenues under Process Variations
Abhishek Das, IEEE
Serkan Ozdemir, IEEE
Gokhan Memik, IEEE
Joseph Zambreno, IEEE
Alok Choudhary, IEEE
Full Article Text:
 
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2007.8
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| Abstract |
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As transistor feature sizes continue to shrink intothe sub-90nm range and beyond, the effects of process variationson critical path delay and chip yields have amplified. A commonconcept to remedy the effects of variation is speed-binning, bywhich chips from a single batch are rated by a discrete range offrequencies and sold at different prices. In this paper, we discussstrategies to modify the number of chips in different bins andhence enhance the profits obtained from them. Particularly, wepropose a scheme that introduces a small Substitute Cacheassociated with each cache way to replicate the data elementsthat will be stored in the high latency lines. Assuming a fixedpricing model, this method increases the revenue by as much as 13.8% without any impact on the performance of the chips.
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 Additional Information
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Index Terms- Computer Architecture, Cache Memories, Process Variations, Fault-tolerant Computing.
Citation:
Abhishek Das, Serkan Ozdemir, Gokhan Memik, Joseph Zambreno, Alok Choudhary,
"Microarchitectures for Managing Chip Revenues under Process Variations,"
IEEE Computer Architecture Letters,
vol. 6,
no. 2,
pp. 29-32,
Jul-Dec,
2007
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