Dynamically Tuning Processor Resources with Adaptive Processing

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December 2003 (Vol. 36, No. 12) pp. 49-58
Dynamically Tuning Processor Resources with Adaptive Processing
David H. Albonesi, University of Rochester
Rajeev Balasubramonian, University of Rochester
Steven G. Dropsho, University of Rochester
Sandhya Dwarkadas, University of Rochester
Eby G. Friedman, University of Rochester
Michael C. Huang, University of Rochester
Volkan Kursun, University of Rochester
Grigorios Magklis, University of Rochester
Michael L. Scott, University of Rochester
Greg Semeraro, University of Rochester
Pradip Bose, IBM T.J. Watson Research Center
Alper Buyuktosunoglu, IBM T.J. Watson Research Center
Peter W. Cook, IBM T.J. Watson Research Center
Stanley E. Schuster, IBM T.J. Watson Research Center

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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MC.2003.1250883
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Abstract
The adaptive processing approach improves microprocessor energy efficiency by dynamically tuning major resources during execution to better match varying application needs. This tuning usually involves reducing a resource's size when its full capabilities are not needed, then restoring the disabled portions when they are needed again.Adaptive processors require few additional transistors. Further, because adaptation occurs only in response to infrequent trigger events, the decision logic can be placed into a low-leakage state until such events occur.
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[1] D.H. Albonesi, "Dynamic IPC/Clock Rate Optimization," Proc. 25th Int'l Symp. Computer Architecture, IEEE CS Press, 1998, pp. 282-292. [2] D.H. Albonesi, "The Inherent Energy Efficiency of Complexity-Adaptive Processors," Proc. 1998 Power-Driven Microarchitecture Workshop, 1998, pp. 107-112. [3] B. Xu and D.H. Albonesi, "A Methodology for the Analysis of Dynamic Application Parallelism and Its Application to Reconfigurable Computing," Proc. SPIE Int'l Symp. Reconfigurable Technology: FPGAs for Computing and Applications, SPIE Press, 1999, pp. 78-86. [4] A. Buyuktosunoglu et al., "A Circuit-Level Implementation of an Adaptive-Issue Queue for Power-Aware Microprocessors," Proc. 11th Great Lakes Symp. VLSI, ACM Press, 2001, pp. 73-78. [5] M.D. Powell et al., "Reducing Leakage in a High-Performance Deep-Submicron Instruction Cache," IEEE Trans. VLSI Systems, vol. 9, no. 1, 2001, pp. 77-89. [6] N.S. Kim et al., "Drowsy Instruction Caches—Leakage Power Reduction Using Dynamic Voltage Scaling and Cache Sub-Bank Prediction," Proc. Int'l Symp. Microarchitecture, IEEE CS Press, 2002, pp. 219-230. [7] D. Ponomarev et al., "Reducing Power Requirements of Instruction Scheduling through Dynamic Allocation of Datapath Resources for Low Power," Proc. Int'l Symp. Microarchitecture, IEEE CS Press, 2001, pp. 90-101. [8] D. Folegnani and A. Gonzalez, "Energy-Effective Issue Logic," Proc. Int'l Symp. Computer Architecture, IEEE CS Press, 2001, pp. 230-239. [9] M.C. Huang, J. Renau, and J. Torrellas, "Positional Adaptation of Processors: Application to Energy Reduction," Proc. Int'l Symp. Computer Architecture, IEEE CS Press, 2003, pp. 157-168. [10] R. Balasubramonian et al., "Memory Hierarchy Reconfiguration for Energy and Performance in General-Purpose Processor Architectures," Proc. 33rd Int'l Symp. Microarchitecture, IEEE CS Press, 2000, pp. 245-257. [11] A.S. Dhodapkar and J.E. Smith, "Managing Multiconfiguration Hardware via Dynamic Working Set Analysis," Proc. Int'l Symp. Computer Architecture, IEEE CS Press, 2002, pp. 233-244. [12] R. Sasanka,C.J. Hughes, and S.V. Adve, "Joint Local and Global Hardware Adaptations for Energy," Proc. Int'l Conf. Architecture Support for Programming Languages and Operating Systems, ACM Press, 2002, pp. 144-155. [13] S. Dropsho et al., "Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power," Proc. 11th Int'l Conf. Parallel Architectures and Compilation Techniques, IEEE CS Press, 2002, pp. 141-152. [14] P. Bose et al., "Early-Stage Definition of LPX: A Low-Power Issue-Execute Processor," Proc. Workshop Power-Aware Computer Systems, Springer, 2002, pp. 1-17. Additional References [1] R. Balasubramonian et al., "Memory Hierarchy Reconfiguration for Energy and Performance in General-Purpose Processor Architectures," Proc. 33rd Int'l Symp. Microarchitecture, IEEE CS Press, 2000, pp. 245-257. [2] M.C. Huang, J. Renau, and J. Torrellas, "Positional Adaptation of Processors: Application to Energy Reduction," Proc. Int'l Symp. Computer Architecture, IEEE CS Press, 2003, pp. 157-168. Additional References [1] W. Yuan et al., "Design and Evaluation of a Cross-Layer Adaptation Framework for Mobile Multimedia Systems," Proc. Multimedia Communications and Networking, SPIE—Int'l Society for Optical Engineering, 2003, pp. 1-13. [2] D.G. Sachs,S.V. Adve,, and D.L. Jones,"Cross-Layer Adaptive Video Coding to Reduce Energy on General-Purpose Processors," Proc. Int'l Conf. Image Processing, Session WA-S2, IEEE Press, 2003, pp. 25-28. [3] R. Sasanka,C.J. Hughes, and S.V. Adve, "Joint Local and Global Hardware Adaptations for Energy," Proc. Int'l Conf. Architecture Support for Programming Languages and Operating Systems, ACM Press, 2002, pp. 144-155.
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Citation: David H. Albonesi, Rajeev Balasubramonian, Steven G. Dropsho, Sandhya Dwarkadas, Eby G. Friedman, Michael C. Huang, Volkan Kursun, Grigorios Magklis, Michael L. Scott, Greg Semeraro, Pradip Bose, Alper Buyuktosunoglu, Peter W. Cook, Stanley E. Schuster, "Dynamically Tuning Processor Resources with Adaptive Processing," Computer, vol. 36, no. 12, pp. 49-58, Dec., 2003

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