Heterogeneous Chip Multiprocessors

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November 2005 (Vol. 38, No. 11) pp. 32-38
Heterogeneous Chip Multiprocessors
Rakesh Kumar, University of California, San Diego
Dean M. Tullsen, University of California, San Diego
Norman P. Jouppi, HP Labs
Parthasarathy Ranganathan, HP Labs

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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MC.2005.379
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Abstract
Heterogeneous (or asymmetric) chip multiprocessors present unique opportunities for improving system throughput, reducing processor power, and mitigating Amdahl's law. On-chip heterogeneity allows the processor to better match execution resources to each application's needs and to address a wider spectrum of system loads-from low to high thread parallelism-with high efficiency.
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[1] K. Olukotun et al., "The Case for a Single-Chip Multiprocessor," Proc. 7th Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS VII), ACM Press, 1996, pp. 2-11. [2] L. Barroso et al., "Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing," Proc. 27th Ann. Int'l Symp. Computer Architecture, IEEE CS Press, 2000, pp. 282-293. [3] E. Grochowski et al., "Best of Both Latency and Throughput," Proc. Int'l Conf. Computer Design, IEEE CS Press, 2004, pp. 236-243. [4] D. Pham et al., "The Design and Implementation of a First-Generation Cell Processor," Proc. Int'l Symp. Solid-State Circuits and Systems, IEEE CS Press, 2005, pp. 184-186. [5] R. Kumar et al., "Single-ISA Heterogeneous Multicore Architectures: The Potential for Processor Power Reduction," Proc. Int'l Symp. Microarchitecture, IEEE CS Press, 2003, pp. 81-92. [6] R. Kumar et al., "Single-ISA Heterogeneous Multicore Architectures for Multithreaded Workload Performance," Proc. Int'l Symp. Computer Architecture, IEEE CS Press, 2004, pp. 64-75. [7] G. Amdahl, "Validity of the Single Processor Approach to Achieving Large-Scale Computing Capabilities," Readings in Computer Architecture, M.D. Hill, N.P. Jouppi, and G.S. Sohi, eds., Morgan Kaufmann, 2000, pp. 79-81. [8] M. Annavaram, E. Grochowski, and J. Shen, "Mitigating Amdahl's Law through EPI Throttling," Proc. Int'l Symp. Computer Architecture, IEEE CS Press, 2005, pp. 298-309. [9] S. Ghiasi, T. Keller, and F. Rawson, "Scheduling for Heterogeneous Processors in Server Systems," Proc. Computing Frontiers, ACM Press, 2005, pp. 199-210. [10] S. Balakrishnan et al., "The Impact of Performance Asymmetry in Emerging Multicore Architectures," Proc. Int'l Symp. Computer Architecture, IEEE CS Press, 2005, pp. 506-517. [11] P. Ranganathan and N.P. Jouppi, "Enterprise IT Trends and Implications on System Architecture Research," Proc. Int'l Conf. High-Performance Computer Architecture, IEEE CS Press, 2005, pp. 253-256. Additional References [1] R. Kumar, N.P. Jouppi, and D. Tullsen, "Conjoined-Core Chip Multiprocessing," Proc. Int'l Symp. Microarchitecture, IEEE CS Press, 2004, pp. 195-206. [2] R. Kumar, V. Zyuban, and D. Tullsen, "Interconnection in Multicore Architectures: Understanding Mechanisms, Overheads, and Scaling," Proc. Int'l Symp. Computer Architecture, IEEE CS Press, 2005, pp. 408-419.
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Index Terms- Multiprocessors, Multicore microprocessors, Chip multiprocessors, CMP, Power-aware computing, System architectures, Heterogeneity Citation: Rakesh Kumar, Dean M. Tullsen, Norman P. Jouppi, Parthasarathy Ranganathan, "Heterogeneous Chip Multiprocessors," Computer, vol. 38, no. 11, pp. 32-38, Nov., 2005

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