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Published Articles >> Table of Contents >> Abstract
April 2007 (Vol. 40, No. 4)
pp. 68-75
Embracing and Extending 20th-Century Instruction Set Architectures
Joe Gebis, University of California, Berkeley
David Patterson, University of California, Berkeley
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MC.2007.124
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| Abstract |
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A vector case study shows how new functionality can be added to extend the 80x86 and PowerPC architectures to support a full vector architecture, primarily by enhancing their multimedia extensions to provide a better model for compilers and an easier-to-understand model for programmers.
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 References
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[1] L. Oliker et al., "Scientific Computations on Modern Parallel Vector Systems," Proc. 2004 ACM/IEEE Conf. Supercomputing (SC 2004), IEEE CS Press, 2004; http://crd.lbl.gov/~oliker/papersSC04.pdf .
[2] C. Kozyrakis and D. Patterson, "Vector vs. Superscalar and VLIW Architectures for Embedded Multimedia Benchmarks," Proc. 35th Int'l Symp. Microarchitecture, IEEE CS Press, 2002, pp. 283–293.
[3] J.E. Smith, G. Faanes, and P. Sugumar, "Vector Instruction Set Support for Conditional Operations," Proc. 27th Int'l Symp. Computer Architecture, ACM Press, 2000, pp. 260–269.
[4] C. Kozyrakis, "Scalable Vector Media-Processors for Embedded Systems," report no. UCB/CSD-02-1183, Univ. of California, Berkeley, May 2002.
[5] D. Abts, S. Scott, and D.J. Lilja, "So Many States, So Little Time: Verifying Memory Coherence in the Cray X1," Proc. Int'l Parallel and Distributed Processing Symp., IEEE CS Press, 2003; www.arctic.umn.edu/papersabts-somanystate.pdf .
[6] J.D. Gee and A.J. Smith, "The Performance Impact of Vector Processor Caches," Proc. 25th Hawaii Int'l Conf. System Sciences, vol. 1, IEEE CS Press, 1992, pp. 437–448.
[7] F. Quintana et al., "Adding a Vector Unit to a Superscalar Processor," Proc. 13th Int'l Conf. Supercomputing, ACM Press, 1999, pp. 1–10.
[8] J.E. Smith, "The Best Way to Achieve Vector-Like Performance? Use Vectors," invited speech, 21st Ann. Int'l Symp. Computer Architecture, IEEE CS Press, 1994; www.engr.wisc.edu/ece/facultysmith_james.html .
[9] R. Uhlig et al., "Intel Virtualization Technology," Computer, vol. 38, no. 5, 2005, pp. 48–56.
[10] E. Witchel, J. Cates, and K. Asanovic, "Mondrian Memory Protection," Proc. 10th Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), ACM Press, 2002, pp. 304–316.
Additional References
[1] M.J. Flynn, "Very High-Speed Computing Systems," Proc. IEEE, Dec. 1966, pp. 1901–1909.
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 Additional Information
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Index Terms- instruction set architectures, PowerPC, vector architecture, SIMD processors
Citation:
Joe Gebis, David Patterson,
"Embracing and Extending 20th-Century Instruction Set Architectures,"
Computer,
vol. 40,
no. 4,
pp. 68-75,
Apr.,
2007
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