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November/December 2004 (Vol. 24, No. 6)   pp. 92-103
Transactional Coherence and Consistency: Simplifying Parallel Hardware and Software

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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2004.91
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Abstract
TCC simplifies parallel hardware and software design by eliminating the need for conventional cache coherence and consistency models and letting programmers parallelize a wide range of applications with a simple, lock-free transactional model.
References
[1] R. Rajwar and J. Goodman, "Transactional Lock-Free Execution of Lock-Based Programs," Proc. 10th Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS 02), ACM Press, 2002, pp. 5-17.
[2] M. Herlihy and J. Moss, "Transactional Memory: Architectural Support for Lock-Free Data Structures," Proc. 20th Int'l Symp. Computer Architecture (ISCA 93), ACM Press, 1993, pp. 289-300.
[3] J. Martinez and J. Torrellas, "Speculative Synchronization: Applying Thread-Level Speculation to Parallel Applications," Proc. 10th Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS 02), ACM Press, 2002, pp. 18-29.
[4] M.K. Chen and K. Olukotun, "The Jrpm System for Dynamically Parallelizing Java Programs," Proc. 30th Int'l Symp. Computer Architecture (ISCA 03), IEEE CS Press, 2003, pp. 434-445.
[5] L. Hammond et al., "Programming with Transactional Coherence and Consistency (TCC)," Proc. 11th Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS 04), ACM Press, 2004, pp. 1-13.
[6] L. Hammond et al., "Transactional Memory Coherence and Consistency," Proc. 31st Int'l Symp. Computer Architecture (ISCA 04), IEEE CS Press, 2004, pp. 102-113.
Additional Information

Citation:  Lance Hammond, Brian D. Carlstrom, Vicky Wong, Michael Chen, Christos Kozyrakis, Kunle Olukotun, "Transactional Coherence and Consistency: Simplifying Parallel Hardware and Software," IEEE Micro, vol. 24,  no. 6,  pp. 92-103,  Nov/Dec,  2004

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