Abstract
This paper presents the designs of two digital circuits in which processing of data (stored in volatile and non-volatile memories) is locally performed and routed; these circuits are referred to as data-centric and therefore, amenable to Near-Memory (NM)operation. Two circuits are proposed; they utilize at logic level a 2-2AOI gate, but with different types of selector. Simulation results using HSPICE are provided for logic data path and memory access performance. Comparison between designs with either a Programmable Metallization Cell (PMC), or a Phase Change Memory (PCM), is assessed; simulation confirms that in most cases of memory operations, a PMC based data-centric circuit has better performance than a PCM-based circuit in terms of delay. The proposed data-centric circuits are evaluated also for implementation of more complex functional blocks (such as adders and encoder) as well as a balanced FIFO merger for sorting application.