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Published Articles >> Table of Contents >> Abstract
Seventh International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT'06)
pp. 44-49
A High-Efficiency Vector Interpolator Using Redundant CORDIC Arithmetic in Power-Aware 3-D Graphics Rendering
Tze-Yun Sung, Chung Hua University, Taiwan
Yaw-Shih Shieh, Chung Hua University, Taiwan
Chun-Wang Yu, Chung Hua University, Taiwan
Hsi-Chin Hsin, National Formosa University, Taiwan
Full Article Text:
 
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PDCAT.2006.7
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| Abstract |
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High performance architectures can be designed for
data intensive and latency tolerant applications by
maximizing the parallelism and pipelining of the
algorithm. The hardware primitives for 3-D rotation
for high throughput 3-D vector interpolation are
presented in this paper. The primitives are based on
the CORDIC algorithm. The proposed architecture of
the 3-D vector interpolator using redundant CORDIC
arithmetic is presented in this paper. The highthroughput
3-D vector interpolator is implemented by
VLSI.
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 Additional Information
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Index Terms- Redundant CORDIC arithmetic, CORDIC algorithm, 3-D vector interpolation, high-throughput.
Citation:
Tze-Yun Sung, Yaw-Shih Shieh, Chun-Wang Yu, Hsi-Chin Hsin,
"A High-Efficiency Vector Interpolator Using Redundant CORDIC Arithmetic in Power-Aware 3-D Graphics Rendering,"
pdcat,
pp. 44-49,
Seventh International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT'06),
2006
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