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Published Articles >> Table of Contents >> Abstract
11th Pacific Rim International Symposium on Dependable Computing (PRDC'05)
pp. 175-182
Compression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation and Test Application Time
Yu Hu, Institute of Computing Technology, CAS Beijing , China
Xiao-Wei Li, Institute of Computing Technology, CAS Beijing , China
Hua-Wei Li, Institute of Computing Technology, CAS Beijing , China
Xiao-Qing Wen, Kyushu Institute of Technology, Japan
Full Article Text:
 
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PRDC.2005.26
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| Abstract |
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Testing chips is very critical to guarantee chips are
fault-free before they are integrated in a system, so as
to increase the reliability of the system. Although fullscan
is a widely adopted design-for-test technique for
LSI design and testing, the need for reducing the test
data Volume, scan-in Power dissipation and test
application Time (VPT) of the full-scan designed chip
is imperative. Based on the analysis of the
characteristics of the variable-to-fixed run-length
coding technique and the random access scan
architecture, this paper presents a novel design scheme
tackling all VPT issues simultaneously. Experimental
results on ISCAS’89 benchmarks have shown on
average 51.2%, 99.5%, 99.3% and 85.5% reduction in
test data volume, average scan-in power dissipation,
peak scan-in power dissipation and test application
time, respectively.
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 Additional Information
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Citation:
Yu Hu, Xiao-Wei Li, Hua-Wei Li, Xiao-Qing Wen,
"Compression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation and Test Application Time,"
prdc,
pp. 175-182,
11th Pacific Rim International Symposium on Dependable Computing (PRDC'05),
2005
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