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Published Articles >> Table of Contents >> Abstract
11th Pacific Rim International Symposium on Dependable Computing (PRDC'05)
pp. 183-192
Partitioned Cache Shadowing for Deep Sub-Micron (DSM) Regime
Heng Xu, Iowa State University, Ames, IA
Arun Somani, Iowa State University, Ames, IA
Full Article Text:
 
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PRDC.2005.48
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| Abstract |
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An important issue in modern cache designs is bridging
the gap between wire and device delays. This warrants the
use of more regular and modular structures to mask wire latencies.
This paper advances the basic concepts of shadow
caching to offer protection against both data corruption
and micro-network disruption in partitioned architectures.
Network disruption is tolerated by sending shadow packet
along a different route than the original packet, whereas the
data corruption problem is addressed by reserving a small
portion of the overall cache capacity for in-cache shadow
space. Our results show that an average of 96% in data error
coverage for Spec2K benchmarks can be achieved and
more than 99% of the transient faults on the underlying
switched micro-network can also be protected while incurring
less than 3% performance degradation in most of the
above benchmarks.
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 Additional Information
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Citation:
Heng Xu, Arun Somani,
"Partitioned Cache Shadowing for Deep Sub-Micron (DSM) Regime,"
prdc,
pp. 183-192,
11th Pacific Rim International Symposium on Dependable Computing (PRDC'05),
2005
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