Area Efficient and Fast Combined Binary/Decimal Floating Point Fused Multiply Add Unit

Ahmed A. Wahba; Hossam A. H. Fahmy

doi:10.1109/TC.2016.2584067

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IEEE Transactions on Computers

Area Efficient and Fast Combined Binary/Decimal Floating Point Fused Multiply Add Unit

Feb. 2017, pp. 226-239, vol. 66

DOI Bookmark: 10.1109/TC.2016.2584067

Authors

Ahmed A. Wahba, Department of Electronics and Electrical Communications Engineering, Cairo University, Giza, Egypt
Hossam A. H. Fahmy, Department of Electronics and Electrical Communications Engineering, Cairo University, Giza, Egypt

Keywords

Adders, Hardware, Delays, Standards, Encoding, Detectors, Decoding, Base 3 LZA, Binary Floating Point, Decimal Floating Point, Fused Multiply Add, Leading Zeros Anticipator, Redundant

Area Efficient and Fast Combined Binary/Decimal Floating Point Fused Multiply Add Unit

Authors

Keywords

Abstract