Abstract
IMEC and Cadence have jointly developed a 3D-DfT architecture that serves both 2.5D- and 3D-SICs. Originally targeting stacks of monolithic logic-only dies, over time this architecture has been extended to include (1) memory-on-logic stacks, (2) complex SOCs, and (3) multi-tower stacks. We have defined and implemented a full automation flow based on Cadence' RTL Compiler and Encounter Test. To demonstrate the capabilities of the 3D-DfT architecture and associated EDA flow, we designed a 3D-DfT Demonstrator circuit as part of an IMEC 3D chip stack nicknamed ‘Vesuvius-3D’. This test vehicle consists of two identical dies of 8.1×8.1mm2 in 65nm CMOS processed by GLOBALFOUNDRIES and IMEC. In this paper, we report on the design, test generation, processing, and pre-bond and post-bond measurement results of this 3D-DfT Demonstrator.