Intra-die process variation aware anomaly detection in FPGAs

Youngok Pino; Vinayaka Jyothi; Matthew French

doi:10.1109/TEST.2014.7035343

2014 IEEE International Test Conference (ITC)

Intra-die process variation aware anomaly detection in FPGAs

Year: 2014, Pages: 1-6

DOI Bookmark: 10.1109/TEST.2014.7035343

Authors

Youngok Pino, University of Southern California, Information Sciences Institute, Arlington, VA, USA
Vinayaka Jyothi, University of Southern California, Information Sciences Institute, Arlington, VA, USA
Matthew French, University of Southern California, Information Sciences Institute, Arlington, VA, USA

Abstract

This work describes a new non-destructive method to determine the presence of anomalies such as Hardware Trojans in physical VLSI layer of FPGA, especially in configurable logic blocks and switch blocks. The detection that accounts for spatially correlated intra-die process variations can be achieved by isolating a suspected region where its device characteristic is inconsistent from ones in the physically nearest regions. This method does not require a golden chip to compare with a chip under test and can be performed without expensive testing equipment. In this paper, we present anomaly implementations and emulations as well as experimental results and analysis on anomaly detection from data obtained from Xili1nx Virtex-4, Virtex-5 and Virtex-6 FPGA devices.

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Intra-die process variation aware anomaly detection in FPGAs

Authors

Abstract

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