Abstract
A new type of logic characterization vehicle (LCV) that optimizes design, test, and diagnosis for yield learning is described. The Carnegie-Mellon LCV (CM-LCV) uses constant-testability theory and logic/layout regularity to create a parameterized design that exhibits both front- and back-end characteristics of a product-like, customer design. Design and test analysis of various CM-LCV designs (one of which has >4M gates) demonstrates that design time and density, test and diagnosis can all be simultaneously improved. For example, conventional ATPG produces test sets that are 2X larger, produce significantly poorer fault-detection and diagnostic characteristics for standard and advanced fault models, and require runtimes that are several orders of magnitude larger than the simple approach used to generate the constant test set for the CM-LCV. On the design side, a fully designed custom layout is 25% smaller than its synthesized, place-and-routed counterpart.